He has over 27 years’ experience in semiconductor processing technology R&D including nearly 14 years in TSMC R&D. His research interests and results cover advanced Cu/low-k interconnect in FEOL and 2.5D/3D advanced packaging in MEOL/BEOL. Was granted over 350 patents and published 11 technical papers.
SmartAiP(TM) for Ultra-Wideband 5G mm-Wave Commutation
SmartPoserTM, a 3D-SiP platform developed by SJSemi that can 3D integrate the entire power delivery subsystem into the package using non-TSV Vertical-InterConnect (V-IC) technology, enabling the integration both the active power dies and the voltage regulating passive SMT components directly underneath the computing die. Here we show the SmartPoserTM derived architecture has successfully resulted in a novel ultra-wideband(UWB) 5G mm-wave AiP for the first time in semiconductor history named SmartAiPTM.
The SmartAiPTM is simulated and measured to have UWB behavior with low return loss of -10dB~-40dB from 24GHz to 43GHz with 12.5dB stable gain, low cross polarization, low back-lobe radiation, as well as nearly identical E and H plane unidirectional radiation patterns thanks to precise wafer-level processing . SmartAiPTM ‘s UWB, low power consumption and slim form factor is a perfect fit for 5G mmWave handset application.
SJ Semiconductor (JiangYin) Corporation
Located in Jiangyin, SJSemi was founded in August 2014. It is the first dedicated 12” advanced Bumping Line in mainland China. SJSemi aims to offer first-class Middle-End-Of-Line (MEOL) manufacturing and testing services and develop the advanced 3D-IC high density integration solutions to satisfy the sophisticated needs of Smart phone, AI, Big Data, Cloud Computing, 5G, AR, etc. It is committed to providing a convenient one-stop service to supply high quality and efficient chips for local and international customers, as well as help strengthen their global competitiveness.